1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a method of manufacturing a semiconductor device in which a butting region can be removed by implanting additional ions into the butting region generated at the boundary between a first area and a second area of a dummy gate electrode.
2. Description of the Related Art
Semiconductor devices such as MOS (Metal Oxide Semiconductor) transistors are a kind of field effect transistors (FET). In MOS transistors, a gate oxide layer and a gate electrode are formed on a semiconductor substrate made of silicon, and source and drain regions are formed in the semiconductor substrate on both sides of the gate electrode. LDD (Lightly Doped Drain) regions with a relatively low concentration are formed inside the source and drain regions.
MOS transistors are classified into N-channel MOS transistors and P-channel MOS transistors based on the conductivity type of the channel. When MOS transistors having both channel types are formed on a single semiconductor substrate, they are referred to as CMOS (Complementary Metal Oxide Semiconductor) transistors.
A typical method of manufacturing a CMOS semiconductor device is described in detail below with reference to the accompanying drawings.
FIGS. 1A to 1I are cross-sectional views illustrating process steps of a conventional method of manufacturing a CMOS semiconductor device.
FIGS. 1A to 1I show an NMOS area and a test area. Since a PMOS area is formed by the use of the same processes as the NMOS area, the PMOS area is omitted from the figures.
First, as shown in FIG. 1A, a semiconductor substrate 10, in which an NMOS area, a PMOS area, an inactive area, and a test area are defined, is prepared. A pad oxide layer 12 and a pad nitride layer 14, which are used for performing an isolation process (ISO) as a subsequent process, are sequentially formed on the entire surface of the semiconductor substrate 10.
Subsequently, as shown in FIG. 1B, a photoresist is deposited on the entire surface of the semiconductor substrate 10 including the pad oxide layer 12 and the pad nitride layer 14 and an exposure process using the photoresist as a mask is performed thereto, thereby forming a first photoresist pattern PR1. Thereafter, a shallow trench isolation (STI) process using the first photoresist pattern PR1 as an isolation (ISO) mask is performed, thereby forming an element isolating layer 18 in the inactive area of the semiconductor substrate 10.
As shown in FIG. 1C, the first photoresist pattern PR1 is removed by performing a stripping process and the pad nitride layer 14 and the pad oxide layer 12 are sequentially removed by performing a cleaning process.
Subsequently, a well region 20 is selectively formed in the NMOS area of the semiconductor substrate 10 by performing a well-ion implantation process using a first well-ion implanting mask.
Thereafter, not shown in the figures, a well region is selectively formed in the PMOS area of the semiconductor substrate 10 by performing the well-ion implantation process using a second well-ion implanting mask. As a result, the well region 20 of the NMOS area is doped with P-type ions and the well region of the PMOS area is doped with N-type ions.
As shown in FIG. 1D, a gate oxide layer 22 is formed by performing a thermal oxidation process or a rapid thermal annealing process to the entire surface of the semiconductor substrate 10 in which the well region 20 is formed.
Subsequently, a polysilicon layer 24 for forming a gate electrode 26 is formed on the entire surface of the semiconductor substrate 10 on which the gate oxide layer 22 is formed.
As shown in FIG. 1E, the polysilicon layer 24 and the gate oxide layer 22 are sequentially etched by performing a photolithography and etching process using a gate-electrode pattern mask. As a result, gate electrodes 26 are formed in the NMOS area and the PMOS area and a dummy gate electrode 99 is formed in the test area. The dummy gate electrode 99 is divided into first and second areas. As shown, the second areas are positioned between the first areas.
The PMOS area and the second areas of the dummy gate electrode 99 are covered using a second photoresist pattern PR2 as a mask. By selectively performing an N-type ion implantation process with a low concentration to the active area of the NMOS area and the first areas of the dummy gate electrode 99, a low-concentration junction region 28 is formed in the NMOS area, and the first areas of the dummy gate electrode 99 are doped with N-type ions with a low concentration.
As shown in FIG. 1F, the NMOS area and the first areas of the dummy gate electrode 99 are covered using a third photoresist pattern PR3 as a mask. By selectively performing an P-type ion implantation process with a low concentration to the active area of the PMOS area and the second areas of the dummy gate electrode 99, a low-concentration junction region is formed in the PMOS area and the second areas of the dummy gate electrode 99 are doped with P-type ions with a low concentration,
Subsequently, as shown in FIG. 1G, HLD (High temperature Low pressure Dielectric) spacers 30 are formed on the sidewalls of the gate electrodes 26 of the NMOS area and the PMOS area, by sequentially performing a deposition process and an etching process.
Thereafter, the PMOS area and the second areas of the dummy gate electrode 99 are covered using a fourth photoresist pattern PR4 as a mask and a part of the low-concentration junction region 28 of the NMOS area is covered using the spacers 30 as a mask. By selectively performing an N-type ion implantation process with a high concentration to the active area of the NMOS area and the first areas of the dummy gate electrode 99, a high-concentration junction region 32 is formed in the NMOS area and the first areas of the dummy gate electrode 99 are doped with N-type ions with a high concentration.
Next, as shown in FIG. 1H, the NMOS area and the first areas of the dummy gate electrode 99 are covered using a fifth photoresist pattern PR5 as a mask and a part of the low-concentration junction region of the PMOS area is covered using the spacers as a mask. By selectively performing a P-type ion implantation process with a high concentration to the active area of the PMOS area and the second areas of the dummy gate electrode 99, a high-concentration junction region is formed in the PMOS area and the second areas of the dummy gate electrode 99 are doped with P-type ions with a high concentration.
As a result, the gate electrode 26 of the NMOS area is doped with N-type ions with a high concentration and the gate electrode of the PMOS area is doped with P-type ions with a high concentration.
Source and drain regions 34 including the low-concentration junction region 28 and the high concentration junction region 32 are formed in the NMOS area and the PMOS area, respectively.
The first areas of the dummy gate electrode 99 are doped with N-type ions with a high concentration and the second areas thereof are doped with P-type ions with a high concentration.
Subsequently, as shown in FIG. 1I, a salicide (Self Aligned Silicide) layer 36 is formed on the high-concentration junction regions 32 of the NMOS and PMOS areas, the gate electrodes 26, and the dummy gate electrode 99.
The semiconductor device formed in this way has the following problems.
FIG. 2 is a diagram illustrating a butting region of a conventional dummy gate electrode.
The salicide layer 36 formed on the gate electrode 26 is an ohmic contact layer and serves to reduce difference in resistance between the gate electrodes 26 and other electrodes when the gate electrodes 26 are connected to the other electrodes. Before the gate electrodes 26 are connected to the other electrodes through the salicide layer, the resistance of the salicide layer 36 must be measured after the salicide layer 36 is formed on the gate electrode 26.
It is possible to measure the resistance of the salicide 36 over the gate electrode 26 by measuring the resistance of the salicide layer 36 formed on the dummy gate electrode 99 in the test area. By measuring the resistance of the salicide layer 36 in the test area, the resistance of the salicide layer 36 formed on the gate electrodes 26 can be indirectly obtained.
When the mask is not accurately aligned on the first areas and the second areas of the dummy gate electrode 99, as shown in FIG. 2, butting regions A, which are not doped with ions, may be formed in the boundaries between the first areas and the second areas.
When the butting regions A are generated in the dummy gate electrode 99, the resistance of the salicide layer 36 formed on the dummy gate electrode 99 varies. Therefore, the resistance of the salicide layer 36 over the gate electrode cannot be accurately measured.